1. Field of the Invention
The present invention relates to a communication semiconductor integrated circuit using a polar modulation scheme such as quadrature amplitude modulation (QAM).
2. Background Art
Currently in a generally used I/Q modulation scheme, modulation is performed such that frequency modulation data is represented as points on X-Y coordinates, the frequency modulation data is converted to intersecting X-Y signals, and the X-Y signals are multiplied by a carrier frequency.
On the other hand, in a polar modulation scheme having been used in recent years, modulation is performed such that frequency modulation data is represented as amplitudes and angles, modulation in an angle direction is performed as frequency modulation by a frequency synthesizer (hereinafter, will be referred to as a phase-locked loop (PLL)), and modulation in an amplitude direction is performed by controlling the gain of a power amplifier (hereinafter, will be referred to as a PA).
In a modulation scheme enabling phase modulation, as described above, each data point is expressed as phase information at a certain point in time.
However, in terms of property, a PLL circuit is a circuit for controlling a frequency and thus cannot directly perform phase modulation with phase data even when the data is fed from the outside.
For this reason, phase modulation is performed in view of the fact that a phase is an integral of a frequency.
In some communication semiconductor integrated circuits for frequency modulation according to the prior art, all-digital PLLs (ADPLLs) are used (for example, see IEEE Trans. Circuits Syst. II Analog Digit. Signal Process vol. 53 No. 3, pp. 225 to 229, March 1996).
In order to obtain a phase shift, a phase change of a unit clock has to be provided as frequency modulation.
In such an ADPLL, substantially all the circuits are operated as digital circuits and the phase data is normalized.
However, a digitally controlled oscillator (DCO) composing the DPLL is controlled by a digital value. The DCO basically has analog characteristics. In other words, a feature of the DCO is an output frequency which is not always kept constant relative to a control value.
Thus in the ADPLL, a coefficient corresponding to gain smoothing is multiplied by the output of a loop filter in order to form a feedback system in which fluctuations in the gain of the DCO and the slope of the gain are stabilized.
When a proper value is obtained, a phase modulation amount obtained by the modulation data of the DCO and a smoothing amount for offsetting the phase modulation amount are equal to each other in the ADPLL. Thus the PLL enables frequency modulation in a wide band including a band outside a loop band.
It is therefore the most important to obtain the correct frequency gain of the DCO to perform correct frequency modulation in a closed loop.
In the prior art, a gain is obtained by adjusting a frequency around a carrier frequency (for example, a detuning frequency is adjusted in Blue Tooth and so on) while using the behaviors of a loop at that time.
Such a scheme is ideal but a modulation scheme enabling wide-band frequency modulation causes the following problems:    (1) Accuracy is sacrificed by modulation based on minute frequency steps.    (2) The gain is not constant in a wide band.